Design of optimized reversible multipliers using KMD gates for DSP applications
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Kamaraj A 1 * , Ilanchezhian P 2 , Vallikkannu M 3 , Thirumal L 4
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1 MSEC, Sivakasi, INDIA2 Department of Information Technology, Sona College of Technology, Salem, INDIA3 Department of English, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, Tamil Nadu, INDIA4 Department of ECE, Varuvan Vadivelan Institute of Technology, Dharmapuri, Tamil Nadu, INDIA* Corresponding Author

Abstract

One kind of logic architecture, known as reversible logic, maps the output and input vectors one-to-one. According to the Landauer’s principle from 1961, if a device is irreversible in its characteristics, then deleting a small amount will cause the release of heat energy of the order of kTln2 joules. Here, T represents the absolute temperature of the environment, and k is referred to as the Boltzmann constant. Quantum logic gates, which each carry out a fundamental unitary operation on 1, 2, or more qubits–two-state quantum systems–can be conceived of as the building blocks of a quantum computer, or as kinfolk’s networks of quantum. Quantum networks need the use of reversible logic components. The multiplication procedure in this study makes use of KMD gates. The KMD gate can be used to create a variety of logic circuits, including AND, half adder, and full adder. The criteria for reversibility, fault tolerance, and universality are satisfied by these gates. This research presents the design and simulation of a unique reversible fault-tolerant Wallace multiplier, Baugh-Wooley multiplier, Vedic multiplier, and minimal complexity multiplier. The above multipliers are designed to obtain the addition and product terms with the least amount of delay and optimal slice utilization for sustainable technology. The complete design of the fundamental reversible logic gates was confirmed using the QCADesigner software version 2.0.3. The current designs of several multipliers are compared in this paper based on a number of parameters, such as garbage output (GO), gate count (GC), quantum cost (QC), area, and constant input (CI). The simulation results show improvements in area, delay, CIs, GO, QC, and GC over currently available architectures.

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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Article Type: Research Article

EUR J SUSTAIN DEV RES, Volume 10, Issue 1, 2026, Article No: em0339

https://doi.org/10.29333/ejosdr/17276

Publication date: 01 Jan 2026

Online publication date: 14 Oct 2025

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Article Downloads: 11

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